Digital Electronics 1 (ET1003) Lab Assignment
School of Electrical & Electronic Engineering

DIGITAL ELECTRONICS 1 2010/2011 Session
Lab Assignment Set No 1:

Design of a BCD decoder for a Common Cathode 7-segment LED

A common output device used for displaying decimal numbers is the 7-segment LED display shown in Fig. 1 below. Each of the segments which is labelled with standard letters from a to g, is an LED (or Light Emitting Diode) arranged physically in a matrix such that a decimal digit is displayed when the appropriate segments are lit. For example to display digit two, the LED segments labelled a,b,g,e and d (as illustrated in Fig 1.) must be lit.

Two types of 7-segment displays are generally available: ‘common cathode’ and ‘common anode’. In the ‘common cathode’ type of 7-segment LED display, a logic High (or 1) must be applied at the segment input pin to light up the segment. For example, to display digit 2 as shown above, logic High must be applied at the input pins of a,b,g,e and d, while the logic levels at f and c must be Low. In the common anode type of 7-segment display, the opposite logic level is required to turn on an LED segment, i.e. a logic Low input will cause the segment to light.

In order to display decimal digits coded in BCD, a BCD-to-7-segment decoder is required as illustrated in fig.2. This device takes BCD inputs and generates at its outputs, the appropriate logic levels for the 7-segment LED display. For example, to display digit ‘2’, the BCD code for decimal 2 which is ‘0010’ must be applied at inputs D C B A of the decoder, with input D being the MSB. The decoder in turn generates the correct logic levels at outputs a, b, c, d, e, f and g so that the correct LED segments are lit to display digit 2.

Task:
Your assignment is to do a paper design of this BCD-to-7-segment decoder for a common cathode display using the least possible number of NAND gates (i.e. an optimum design). You are to assume that only BCD numbers are applied to the inputs of the decoder, i.e. you should take advantage of don’t care conditions. Your solutions must show all the design steps taken, i.e. a description of the task, requirements definition, design approaches such as truth-table(s), simplification using K-maps or Boolean theorems, and the implementation (circuit diagrams) using standard logic symbols. Use a Truth-table format as shown below.

On completion of your paper design, you should use NI Multsim and simulate your circuit to verify that your solution works. You are to demonstrate this simulation and submit the simulation file to your Lecturer by Week 12 during your Lab or Tutorial lesson.

Assessment Distribution
Paper Design: 50%
Simulation File: 30%
Demo & Interview: 20 %
____________________________________________________

Truth-table Answer:

K-map answer:

implementation (circuit diagrams) Ans:

Multisims circuit implementation (circuit diagrams) Ans:

download link for multisim circuit implementation

http://www.mediafire.com/?si92mog4v47okk4

____________________________________________________

School of Electrical & Electronic Engineering

Laboratory Test

Instructions to Students

1. Read all the instructions and questions carefully.

2. You are expected to work out your solutions on paper before the day of the test. Marks are given for all the preparatory work, accordingly.

3. Bring your Notebook, (installed with NI Multisim), completed test paper and Multisim simulation file with you on the day of the test.

4. You are required to demonstrate your design to your Lecturer in the laboratory according to the instructions given in the test paper.

5. All efforts have been made to ensure that the ICs, the wires and the digital trainer are fully functional. If you believe that an IC or anything else is faulty, inform your Lecturer and it will be replaced.

6. No other help whatsoever will be given to you in getting your circuit working.

There are 7 pages in this Laboratory Test paper.

Laboratory Test: A 2-bit Adder Circuit

A two bit Adder is a combinational circuit which is able to add two sets of 2-bit numbers A₁ A₀ & B₁ B₀ to produce a sum result which can be up to 3 bits S₂ S₁ S₀. Figure 1 below illustrates.

As an example, the table below shows a typical set of results for input data as given.

	Bit 2	Bit 1	Bit 0	Decimal
Number A Number B		1¹	1	= 3
Number A Number B	+	1	1	= 3
Sum	1	1	0	= 6

Your tasks in this Lab Test is to design, build and test this 2-bit Adder circuit in a number of sequenced steps starting from a simple half adder circuit, progressing to a full adder circuit and finally to a 2-bit Adder. Marks will be given progressively at every stage of the test.

Preparatory Work

The following Sections must be completed before you come for the Laboratory Test

The ICs given to you for this Lab Test are as follows:

IC Type	Number given
7408 or 74LS08	1 pc
7432 or 74LS32	1 pc
7486 or 74LS86	1 pc

Section A: Half Adder

A Half Adder adds only two bits A0 and B0 to produce a Sum output S₀ and a Carry-out output Cout. Complete the truth table for the Half Adder given below.

Inputs		Outputs
B₀	A₀	S₀	C_out
0	0
0	1
1	0
1	1

Marks Allocated:	5 Marks
Marks Awarded:	/ 5 Marks

From the truth table you have completed, implement the Half Adder circuit using the least possible number of gates and ICs. Draw your circuit in the blank space given below. You are also required to build this circuit and demonstrate its workability to your Lecturer during the Lab Test.

Marks Allocated :	30 Marks
Correct Circuit	/ 5 marks
Working Circuit	/ 25 marks

Section B: Full Adder Circuit

The addition of the upper set of bits B1 and A1 requires a 3-bit input as it also includes the carry bit generated from the previous addition, i.e. carry over from the addition of A0 and B0. This requires what is called a full adder, a circuit that adds 3 bits, A1, B1 and the carry-input Cin. This full adder may be designed using the traditional combinational logic approach, using the Truth Table ---> Boolean expressions ---> Karnaugh mapping approach as taught in your lectures. However for this Lab Test, the full adder will not be built using this approach but instead from the use of 2 half adders and a 2-input Or gate connected as shown in the block diagram below. This method results in a simpler circuit for the Full Adder circuit. Using the block diagram, draw your circuit below and on the day of your test, construct and demonstrate its workability to your Lecturer

Marks Allocated :	35 Marks
Correct Circuit	/ 5 marks
Working Circuit	/ 30 marks

Section C: 2 Bit Adder Circuit

The 2-Bit Adder circuit can be constructed using a Half Adder connected to a Full adder as shown in the block diagram below. Using this block diagram, complete the circuit of your 2-bit adder circuit in the blank space provided. Using NI Multisim, capture your completed circuit and save it to your Notebook. In the event that you are unable to get your circuit working on the trainer, you will be required to demonstrate its workability using Multisim to qualify for the marks under “Correct Circuit”. On your test date, construct this circuit on your logic trainer. Hence verify its operation in the presence of your Lecturer by completing the truth table given in the following page. Note that for this circuit, you are required to connect the 2-Bit Adder outputs to one of the 7-Segment digital display on the logic trainer.